Field Programmable Gate Array development

Field Programmable Gate Array development

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Field Programmable Gate Array development

Objectves:

• To create System Verilog (SV) design source descriptions for the various component parts of a Bit Error Rate Tester system for use in the testing of a digital communication system.

• To perform simulations of individual design modules using SV test-modules and the Vivado® Simulator.
• To perform simulations of the complete BERT design top-level module using a SV test-module and the Vivado® Simulator.

• Synthesise and Implement the BERT system, targeting a Field Programmable Gate Array development board (Artix-7 FPGA on Digilent Basys3 development board).

• To perform post-implementation timing simulations of an individual module in order to verify correct operation after implementation.

• Demonstrate the operation of the FPGA implementation of the BERT using the development board by means of a so-called ‘loop-back’ test, and optionally, using a simple visible light communication link.

Learning Outcomes:

See Assignment Specification document:

‘EN0720_KD7020_assignment_2017_18_Specification.docx’.

Software and Hardware Resources:

• Xilinx Vivado ® FPGA/CPLD Design Suite. Available in labs E204/206 and as a free download (Vivado HLS WebPACK Edition) from: //www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

• Digilent Incorporated ‘Basys3’ Artix-7 FPGA Development Board. Reference Manual. Supporting Documentation (available on eLearning portal)

• Power point presentation on Register Transfer Level Design using the System Veilog hardware description language.

Total number of marks available: 310

Description of the BERT System

Figure 1a, below, shows a top-level block diagram of the Bit Error Rate Tester System and figure 1b shows the corresponding physical layout of the Basys3 development board. The system outputs a continuous stream of Manchester Encoded data bits on the ‘man_tx’ output pin, this signal is transmitted via the Visible Light Communication channel shown on the diagram. The received signal from the VLC is fed into the ‘man_rx’ input of the receiver part of the system, where it is decoded to produce the original transmitted data bits (RNRZ). By a process of synchronisation and comparison, the BERT system determines the number of bits that are received without error, for consecutive bursts of 1000 data bits, and displays this information on the 4-digit, 7-segment display.

Synchronisation between the transmitted and received Non-Return-to-Zero (NRZ) data bits is achieved by manually adjusting the delay applied to the transmitted NRZ data bits, via the ‘Delay’ input switches, until a LED (SyncLED) indicates that synchronisation is achieved.

The system is driven by a 100MHz crystal clock and an active-high reset push button, when pressed, resets the entire system.

The highest data bit-rate of the system is one tenth of the master clock frequency, i.e. 10MBits/second. It may be necessary to reduce this data rate in order to perform a test with a simple VLC link having a lower bandwidth.

This assignment involves the design, verification and implementation of the BERT system using a Field Programmable Gate Array (FPGA) device, this is achieved through a series of guided tasks. In addition, the characteristics of the VLC channel will be modelled and investigated by means of mixed-signal simulation.

Vcc

Visible Light

man_tx

MARKETING COMMUNICATIONS DISCUSSION AND BRIEF

Communication

man_rx

Channel

rst

Manchester Data

Manchester Data

clock

Transmitter

Reciever

RNRZ

Error Control

nrz

NRZ* Data Stream

NRZD

Delay

Compare

Delay

Recovered NRZ Data Stream

Delayed NRZ

Match Count (BCD)

SyncLED

The display shows the number

ofcorrectlyreceiveddata bits

(Nc) in consecutive bursts of

1000 bits.

NRZ* -­‐ Non-­‐Return to Zero

Bit-­‐Error-­‐Rate (%) = (1000 – Nc)/10